| US 7,599,234 B2 | ||
| Semiconductor memory devices having signal delay controller and methods performed therein | ||
| Jeong-Sik Nam, Seoul (Korea, Republic of); and Ho-Sung Song, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd, Gyeonggi-Do (Korea, Republic of) | ||
| Filed on Feb. 09, 2006, as Appl. No. 11/349,995. | ||
| Claims priority of application No. 10-2005-0012300 (KR), filed on Feb. 15, 2005. | ||
| Prior Publication US 2006/0193171 A1, Aug. 31, 2006 | ||
| Int. Cl. G11C 11/063 (2006.01) | ||
| U.S. Cl. 365—194 [365/230.06; 365/189.17] | 16 Claims |
| 1. A semiconductor memory device including at least one memory cell array, the memory cell array having memory cells disposed
at intersections of rows and columns, the device comprising:
at least one decoder configured to select at least one of at least one row and at least one column associated with at least
one memory cell; and
at least one signal delay controller configured to control a delay of an activation signal applied to the at least one of
row and column by the at least one decoder in response to a block control signal based on at least one of a position of the
at least one memory cell associated with the selected at least of one of row and column and a line loading capacitance value
of the selected memory cell,
wherein the at least one signal delay controller equalizes access times for accessing memory cells regardless of a position
of the memory cells within the memory cell array.
|