US 7,599,231 B2
Adaptive regulator for idle state in a charge pump circuit of a memory device
Marco Passerini, Lozza (Italy); Stefano Sivero, Capriate (Italy); Andrea Sacco, Alessandria (Italy); and Monica Marziani, Arcore (Italy)
Assigned to Atmel Corporation, San Jose, Calif. (US)
Filed on Oct. 11, 2006, as Appl. No. 11/548,319.
Prior Publication US 2008/0089140 A1, Apr. 17, 2008
Int. Cl. G11C 7/00 (2006.01)
U.S. Cl. 365—189.11  [365/189.01; 365/226; 365/229; 327/390] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory element coupled to a modify node, a first node, and a read node, the read node to receive a voltage having a predetermined voltage level and to selectively provide information stored in the at least one memory element, the first node having a first capacitance and a first capacitance voltage level; and
an adaptive voltage generator coupled to the modify node to selectively modify information in the at least one memory element coupled to the modify node, wherein the adaptive voltage generator is configured to maintain the first node and the modify node at the predetermined voltage level when switching between a modify operation and a read operation in the at least one memory element.