US 7,599,166 B2
Multilayer chip capacitor
Byoung Hwa Lee, Kyungki-do (Korea, Republic of); Hae Suk Chung, Seoul (Korea, Republic of); Dong Seok Park, Seoul (Korea, Republic of); Min Cheol Park, Kyungki-do (Korea, Republic of); Sang Soo Park, Kyungki-do (Korea, Republic of); and Sung Kwon Wi, Seoul (Korea, Republic of)
Assigned to Samsung Electro-Mechanics Co., Ltd., Kyungki-Do (Korea, Republic of)
Filed on Nov. 14, 2006, as Appl. No. 11/598,672.
Claims priority of application No. 10-2005-0110394 (KR), filed on Nov. 17, 2005; and application No. 10-2006-0099092 (KR), filed on Oct. 11, 2006.
Prior Publication US 2007/0109717 A1, May 17, 2007
Int. Cl. H01G 4/00 (2006.01); H01G 4/005 (2006.01)
U.S. Cl. 361—306.3  [361/303] 40 Claims
OG exemplary drawing
 
1. A multilayer chip capacitor comprising:
a capacitor body having a plurality of dielectric layers stacked one atop another;
a plurality of internal electrode layers separated from each other in the capacitor body by the dielectric layers, wherein each of the internal electrode layers has one or two leads extending to an outer surface of the capacitor body, and includes at least one coplanar electrode plate; and
a plurality of external electrodes arranged on the outer surface of the capacitor body and electrically connected to the internal electrode layers via the leads,
wherein the internal electrode layers constitute a plurality of blocks stacked repeatedly one atop another, each of the blocks including a plurality of the internal electrode layers which are arranged successively in a stacking direction;
each of the electrode plates has one lead extending to a face of the capacitor body;
the leads extending to the face of the capacitor body are arranged in a zigzag shape along the stacking direction; and
the leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other,
wherein the total number of the external electrodes is eight, and
wherein each of the blocks includes six of the internal electrode layers which are arranged successively in the stacking direction.