| US 7,598,765 B2 | ||
| Redundant configuration memory systems and methods | ||
| Satwant Singh, Fremont, Calif. (US); and Chan-Chi Jason Cheng, Fremont, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Feb. 28, 2007, as Appl. No. 11/680,526. | ||
| Prior Publication US 2008/0204073 A1, Aug. 28, 2008 | ||
| Int. Cl. H03K 19/003 (2006.01) | ||
| U.S. Cl. 326—10 | 12 Claims |
| 1. A programmable logic device comprising:
a plurality of configuration memory cells; and
at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide
to at least one defective configuration memory cell to maintain a stored value of the configuration data within the at least
one defective configuration memory cell,
the at least one spare memory cell including at least one driver to drive the configuration data stored in the at least one
spare memory cell to the at least one defective configuration memory cell during a user mode of operation to maintain a proper
configuration data value within the at least one defective configuration memory cell;
a plurality of bitlines;
a plurality of wordlines;
a data shift register adapted to provide the configuration data to the plurality of configuration memory cells via the bitlines;
and
an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines.
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