a semiconductor substrate having a cell region and a resistor region;

an isolation layer disposed on the semiconductor substrate to define a cell active region in the cell region and resistor active regions in the resistor region;

an insulating layer disposed on the cell active region, the insulating layer being self-aligned with the isolation layer;

a stacked gate structure disposed on the insulating layer, the stacked gate structure including a floating gate electrode, an intergate dielectric, and a control gate electrode that are sequentially stacked;

first conductive layer patterns disposed on the resistor active regions, the first conductive layer patterns being self-aligned with the isolation layer;

a second conductive layer pattern disposed on the isolation layer between the first conductive layer patterns, the second conductive layer pattern covering the first conductive layer patterns, the second conductive layer pattern and the first conductive layer patterns forming a load resistor pattern;

an interlayer insulating layer disposed over the load resistor pattern;

resistor contact holes exposing the load resistor pattern over the resistor active regions, the resistor contact holes formed through the interlayer insulating layer, wherein the resistor contact holes are not formed on the isolation layer; and

resistor contact plugs filling the resistor contact holes to contact the load resistor pattern, wherein bottom surfaces of the resistor contact plugs are positioned at a lower level than a top surface of the second conductive layer pattern.