| US 7,598,168 B2 | ||
| Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer | ||
| Sang-cheol Han, Seoul (Korea, Republic of); Kyoung-woo Lee, Seoul (Korea, Republic of); and Mi-young Kim, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jan. 11, 2005, as Appl. No. 11/33,208. | ||
| Claims priority of application No. 10-2004-0008065 (KR), filed on Feb. 06, 2004. | ||
| Prior Publication US 2005/0176243 A1, Aug. 11, 2005 | ||
| Int. Cl. H01L 21/4763 (2006.01); H01L 21/461 (2006.01) | ||
| U.S. Cl. 438—637 [257/E21.251; 257/E21.255; 257/E21.301; 257/E21.579; 438/745] | 25 Claims |
| 1. A method of forming a dual damascene interconnection comprising the ordered steps of:
(a) sequentially forming on a surface of a semiconductor substrate on which a lower metal wiring is formed a first etch stop
layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer;
(b) etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via;
(c) forming a sacrificial layer of HSQ or SOG within the via, wherein said HSQ or SOG sacrificial layer is a different material
than the first intermetal dielectric, the second intermetal dielectric, or the capping layer;
(d) etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench;
(e) removing portions of the sacrificial layer remaining within the via and on the capping layer using an etchant composition
consisting essentially of NH4F, HF, H2O and a surfactant; and,
(f) forming an upper metal wiring within a dual damascene pattern including the via and the trench.
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