| US 7,596,733 B2 | ||
| Dynamically reconfigurable shared scan-in test architecture | ||
| Rohit Kapur, Cupertino, Calif. (US); Nodari Sitchinava, San Mateo, Calif. (US); Samitha Samaranayake, San Mateo, Calif. (US); Emil Gizdarski, Santa Clara, Calif. (US); Frederic J. Neuveux, Meylan (France); Suryanarayana Duggirala, San Jose, Calif. (US); and Thomas W. Williams, Boulder, Colo. (US) | ||
| Assigned to Synopsys, Inc., Mountain View, Calif. (US) | ||
| Filed on Jul. 23, 2008, as Appl. No. 12/178,517. | ||
| Application 12/178517 is a continuation of application No. 10/856105, filed on May 28, 2004, granted, now 7,418,640. | ||
| Prior Publication US 2008/0301510 A1, Dec. 04, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—726 [714/732] | 7 Claims |
| 1. A method for performing a scan operation on a test design, the method being implementable using a computer, the method
comprising:
mapping a first set of scan inputs to a first plurality of scan chains on a first shift cycle;
mapping a second set of scan inputs to a second plurality of scan chains on a second shift cycle;
analyzing scan outputs of the first and second pluralities of scan chains based on the first and second sets of scan inputs,
respectively; and
generating results based on analyzed scan outputs, the results identifying any occurrence of a fault,
wherein dynamically using the first and second shift cycles during a scan increases a probability that a test pattern can
be applied to the test design without conflict.
|