| US 7,596,174 B2 | ||
| Equalizing a transmitter | ||
| Karthisha S. Canagasaby, Santa Clara, Calif. (US); Muraleedhara Navada, Santa Clara, Calif. (US); and Sanjay Dabral, Palo Alto, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 28, 2005, as Appl. No. 11/237,118. | ||
| Prior Publication US 2007/0071083 A1, Mar. 29, 2007 | ||
| Int. Cl. H04B 7/30 (2006.01) | ||
| U.S. Cl. 375—229 | 25 Claims |
| 1. An apparatus comprising:
a filter having a plurality of delay elements to generate a plurality of tap delays based on an incoming signal;
a plurality of multiplexers coupled to the plurality of tap delays;
a plurality of drivers each coupled to one of the plurality of multiplexers to generate a current controlled by the one of
the plurality of tap delays passed by the associated multiplexer; and
a controller to control each of the plurality of multiplexers to pass one of the plurality of tap delays, wherein the passed
tap delays are to be summed to generate a signal for transmission on an interconnect.
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