| US 7,596,048 B2 | ||
| Memory system and method of controlling the same | ||
| Yohei Kamiyama, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 27, 2008, as Appl. No. 12/38,349. | ||
| Claims priority of application No. 2007-050435 (JP), filed on Feb. 28, 2007. | ||
| Prior Publication US 2008/0219078 A1, Sep. 11, 2008 | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—226 [365/227] | 20 Claims |
| 1. A memory system receiving a power supply from a host device comprising:
a non-volatile semiconductor memory; and
a controller for controlling writing and reading data to and from the semiconductor memory, in response to a request from
the host device,
wherein the controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current
supplied from the power supply, the n currents having n values that gradually increase from the first to n-th (n is a natural
number equal to or larger than 2);
when an amount of each of the n currents is deducted from an amount of a current supplied from the power supply in order from
the first to n-th values, the controller determines whether or not the corresponding voltage of the power supply falls below
a preset detection voltage; and
after detecting that a current having the p-th (p is a natural number between 2 and n, inclusive) one of the n values makes
the corresponding voltage of the power supply to fall below the detection voltage, the controller operates so that the memory
system consumes a current having a value smaller than the p-th one of the n values.
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