| US 7,596,044 B2 | ||
| Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof | ||
| Gong-Heum Han, Hwasung-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-Si (Korea, Republic of) | ||
| Filed on Jan. 07, 2008, as Appl. No. 11/969,947. | ||
| Claims priority of application No. 10-2007-0002091 (KR), filed on Jan. 08, 2007. | ||
| Prior Publication US 2008/0165603 A1, Jul. 10, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—205 [365/207] | 9 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array including memory cells arranged in rows and columns;
a row decoder selecting one of the rows and activating the selected row;
a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns;
a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier; and
a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense
amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch
type mode after the predetermined period.
|