| US 7,596,042 B2 | ||
| Semiconductor memory device having a plurality of chips and capability of outputting a busy signal | ||
| Hiroshi Nakamura, Fujisawa (Japan); Kenichi Imamiya, Tokyo (Japan); and Ken Takeuchi, Stanford, Calif. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 02, 2007, as Appl. No. 11/906,379. | ||
| Application 11/906379 is a division of application No. 10/949274, filed on Sep. 24, 2004, granted, now 7,542,323. | ||
| Application 10/949274 is a continuation of application No. 10/754993, filed on Jan. 08, 2004, granted, now 6,990,003. | ||
| Application 10/754993 is a continuation of application No. 10/185645, filed on Jun. 28, 2002, granted, now 6,680,858. | ||
| Claims priority of application No. 2001-198132 (JP), filed on Jun. 29, 2001; application No. 2001-377408 (JP), filed on Dec. 11, 2001; and application No. 2002-159518 (JP), filed on May 31, 2002. | ||
| Prior Publication US 2008/0080269 A1, Apr. 03, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—191 [365/185.15; 365/185.16; 365/201] | 5 Claims |
| 1. A semiconductor memory system comprising:
a first semiconductor memory device including a first circuit; and
a second semiconductor memory device including a second circuit;
wherein the second circuit is configured to detect a first signal affected by a first busy state of the first semiconductor
memory device, and the first circuit is configured to detect a second signal affected by a second busy state of the second
semiconductor memory device, and
wherein the first signal reflects a detection result by the first circuit and, a third busy state is output by a status read
operation, and the third busy state reflects the detection result.
|