| US 7,596,027 B2 | ||
| Semiconductor storage device having page copying function | ||
| Koichi Kawai, Yokohama (Japan); Kenichi Imamiya, Tokyo (Japan); and Hiroshi Nakamura, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 21, 2007, as Appl. No. 12/4,546. | ||
| Application 12/004546 is a continuation of application No. 11/582065, filed on Oct. 17, 2006, granted, now 7,315,473, filed on Jan. 01, 2008. | ||
| Application 11/582065 is a continuation of application No. 11/328681, filed on Jan. 09, 2006, granted, now 7,130,217. | ||
| Application 11/328681 is a continuation of application No. 11/219193, filed on Sep. 02, 2005, granted, now 7,082,054. | ||
| Application 11/219193 is a continuation of application No. 10/699398, filed on Oct. 31, 2003, granted, now 7,016,228. | ||
| Application 10/699398 is a continuation of application No. 10/194337, filed on Jul. 12, 2002, granted, now 6,661,706. | ||
| Claims priority of application No. 2001-216980 (JP), filed on Jul. 17, 2001. | ||
| Prior Publication US 2008/0181005 A1, Jul. 31, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.12; 365/185.11] | 40 Claims |
| 1. A method of accessing a nonvolatile semiconductor memory device comprising a nonvolatile memory cell array having first
and second pages, the nonvolatile semiconductor memory device further comprising a latch circuit coupled to the memory cell
array, the method comprising:
supplying a first command, then supplying a first column address, then supplying a first row address for a first page, and
then supplying a second command to cause transfer of data stored in the first page to the latch circuit; after the transfer
is completed, supplying a third command, then supplying a second column address, then supplying a second row address for a
second page, then supplying a superseding data to the nonvolatile semiconductor memory device to change a portion of the transferred
data in the latch circuit while allowing the other portion of the transferred data to stay unchanged in the latch circuit;
and
then supplying a fourth command to initiate programming into the second page according to the superseding data and the other
portion of the transferred data in the latch circuit,
wherein at least a portion of the superseding data is stored in the second column address in the second page after the programming
is completed, and the first page is different from the second page.
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