| US 7,596,020 B2 | ||
| Multi-level nonvolatile semiconductor memory device capable of discretely controlling a charge storage layer potential based upon accumulated electrons | ||
| Michio Nakagawa, Kanagawa-ken (Japan); and Koji Sakui, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 31, 2006, as Appl. No. 11/461,207. | ||
| Claims priority of application No. 2005-222699 (JP), filed on Aug. 01, 2005. | ||
| Prior Publication US 2007/0035996 A1, Feb. 15, 2007 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.03 [365/185.17; 365/185.18] | 8 Claims |
| 1. A multi-level programmable nonvolatile semiconductor memory device comprising:
a charge accumulation layer;
a control gate which biases a potential to the charge accumulation layer, wherein
the potential of the charge accumulation layer is controlled to be between the interval of 85 mV and 125 mV.
|