US 7,595,824 B2
Signal processor, data processor, and solid state image sensor
Yoshitaka Egawa, Kanagawa-ken (Japan); and Yasushi Nishimura, Kanagawa-ken (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jul. 27, 2005, as Appl. No. 11/190,118.
Claims priority of application No. 2004-220462 (JP), filed on Jul. 28, 2004.
Prior Publication US 2006/0022862 A1, Feb. 02, 2006
Int. Cl. H04N 5/217 (2006.01); H04N 5/228 (2006.01); H03M 1/12 (2006.01)
U.S. Cl. 348—241  [348/222.1; 341/155] 20 Claims
OG exemplary drawing
 
1. A signal processor comprising:
a timing generation circuit configured to generate a noise canceling period within a horizontal scanning period for a noise canceling circuit to cancel noise imposed on an analog signal stored in a pixel unit;
an analog to digital conversion circuit configured to carry out analog to digital conversion of a signal resulting from noise cancellation;
a first line memory configured to store a digital signal resulting from analog to digital conversion;
a digital signal processor configured to process the digital signal stored in the first line memory;
an output circuit configured to output a signal resulting from signal processing by the digital signal processor;
a second line memory configured to store a digital signal for a shorter period than the horizontal scanning period and be disposed before the output circuit; and
a control circuit configured to control the second line memory so as to cause the output circuit to output the signal stored in the second line memory during a period other than the noise canceling period in the horizontal scanning period.