| US 7,595,793 B2 | ||
| Plain display apparatus, display control circuit and display control method, that divide plural signal lines in blocks | ||
| Kiyoshi Hidaka, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 30, 2006, as Appl. No. 11/341,522. | ||
| Claims priority of application No. 2005-023889 (JP), filed on Jan. 31, 2005. | ||
| Prior Publication US 2006/0187162 A1, Aug. 24, 2006 | ||
| Int. Cl. G09G 5/00 (2006.01) | ||
| U.S. Cl. 345—204 [345/98] | 16 Claims |
| 1. A plain display apparatus, comprising:
a plurality of display elements formed in vicinity of signal lines and scanning lines disposed in a matrix form; and
a signal line drive circuit which switches order of supplying pixel data to the signal lines at random for each horizontal
line,
wherein the signal line drive circuit includes:
a pixel data switching circuit which controls switching of whether the pixel data is supplied to the signal lines in each
block having a pluralitly of signal lines;
a random number generating circuit which generates the random numbers or the pseudo-random numbers; and
an order setting circuit which sets the order that the pixel data switching circuit supplies pixel data to the signal lines
in each block based on the random numbers or the pseudo-random numbers generated by the random generating circuit; and wherein
the random number generating circuit includes:
a prime number counter which conducts a count operation by using a certain prime number as a reference; and
a random value output circuit which outputs random values different from each counter value of the prime number counter;
wherein the order setting circuit sets the order that the pixel data switching circuit supplies the pixel data to the signal
lines in each block based on the random values.
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