a first LC oscillator that generates at least one first clock signal;

a second LC oscillator that generates at least one second clock signal, wherein the at least one first and second clock signals form I/Q clock signals; and

a mismatch compensator that compensates for phase and amplitude mismatches of the I/Q clock signals, wherein the mismatch compensator includes:

an amplitude mismatch detector that detects a first amplitude associated with the at least one first clock signal and a second amplitude associated with the at least one second clock signal,

a transconductor that receives the detected first and second amplitudes and generates a current signal that represents a difference between the first and second amplitudes, and

a capacitor that converts the current signal received from the transconductor into a voltage signal, wherein the voltage signal is provided to configure an operation of the second LC oscillator.