| US 7,595,678 B2 | ||
| Switched-capacitor circuit | ||
| Zhiheng Cao, Dallas, Tex. (US); and Shouli Yan, Austin, Tex. (US) | ||
| Assigned to The Board of Regents, University of Texas System, Austin, Tex. (US) | ||
| Filed on Sep. 11, 2007, as Appl. No. 11/853,509. | ||
| Claims priority of provisional application 60/825230, filed on Sep. 11, 2006. | ||
| Prior Publication US 2008/0061858 A1, Mar. 13, 2008 | ||
| Int. Cl. G06F 7/64 (2006.01) | ||
| U.S. Cl. 327—337 [327/96] | 7 Claims |
| 1. A switched-capacitor circuit comprising:
a first pair of differential inputs and a second pair of differential inputs;
a p-channel switched-capacitor integrator having a set of p-channel input transistors;
a first pair of sampling capacitors and a first pair of integration capacitors, wherein each of said first pair of sampling
capacitors is selectively connected to one of said first pair of differential inputs or one of said p-channel input transistors
via a first set of switches;
an n-channel switched-capacitor integrator having a set of n-channel input transistors, wherein said p-channel switched-capacitor
integrator and said n-channel switched-capacitor integrator function together in a push-pull fashion such that a required
transconductance as well as width and drain current of said n-channel and p-channel input transistors are reduced by half;
and
a second pair of sampling capacitors and a second pair of integration capacitors, wherein each of said second pair of sampling
capacitors is selectively connected to one of said second pair of differential inputs or one of said n-channel input transistors
via a second set of switches.
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