a first switching transistor and a first output transistor which are serially connected between a fixed-voltage terminal that is set to a fixed voltage and said first output terminal;

a second switching transistor and a second output transistor which are serially connected between said fixed-voltage terminal and said second output terminal;

a first bias transistor and a second bias transistor which are provided in parallel with said first switching transistor and said second switching transistor, respectively, and each of which generates a predetermined bias current; and

a second bias circuit which biases the control terminals of said first bias transistor and said second bias transistor at a predetermined second voltage,

wherein a pair of the differential signals to be transmitted are input to the control terminals of said first switching transistor and said second switching transistor;

wherein the control terminals of said first output transistor and said second output transistor are biased at a predetermined first voltages;

wherein said second bias circuit comprises a third transistor, the control terminal of which is connected to the control terminals of said first bias transistor and said second bias transistor such that they share a common control terminal;

and wherein a predetermined second bias current is supplied to a path including said third transistor;

and wherein the control terminal of said third transistor is connected to a node on a path for the second bias current.