| US 7,595,659 B2 | ||
| Logic cell array and bus system | ||
| Martin Vorbach, München (Germany); Frank May, München (Germany); Dirk Reichardt, München (Germany); Frank Lier, München (Germany); Gerd Ehlers, Grasbrunn (Germany); Armin Nückel, Neupotz (Germany); Volker Baumgarte, München (Germany); Prashant Rao, München (Germany); and Jens Oertel, Bad Bergazabern (Germany) | ||
| Assigned to Pact XPP Technologies AG, Munich (Germany) | ||
| Appl. No. 10/398,546 PCT Filed Oct. 08, 2001, PCT No. PCT/EP01/11593 § 371(c)(1), (2), (4) Date Jan. 20, 2004, PCT Pub. No. WO02/29600, PCT Pub. Date Apr. 11, 2002. |
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| Claims priority of application No. PCT/EP00/10516 (WO), filed on Oct. 09, 2000; application No. 101 10 530 (DE), filed on Mar. 05, 2001; application No. 101 11 014 (DE), filed on Mar. 07, 2001; application No. 101 35 210 (DE), filed on Jul. 24, 2001; application No. 101 35 211 (DE), filed on Jul. 24, 2001; application No. 101 39 170 (DE), filed on Aug. 16, 2001; application No. 101 42 231 (DE), filed on Aug. 29, 2001; application No. 101 42 894 (DE), filed on Sep. 03, 2001; application No. 101 42 903 (DE), filed on Sep. 03, 2001; application No. 101 42 904 (DE), filed on Sep. 03, 2001; application No. 101 44 732 (DE), filed on Sep. 11, 2001; application No. 101 44 733 (DE), filed on Sep. 11, 2001; application No. 101 45 792 (DE), filed on Sep. 17, 2001; application No. 101 45 795 (DE), filed on Sep. 17, 2001; application No. 101 46 132 (DE), filed on Sep. 19, 2001; and application No. PCT/EP01/11299 (WO), filed on Sep. 30, 2001. | ||
| Prior Publication US 2004/0128474 A1, Jul. 01, 2004 | ||
| Int. Cl. H03K 19/177 (2006.01); G06F 7/52 (2006.01); G06F 15/00 (2006.01) | ||
| U.S. Cl. 326—39 [326/38; 326/41; 708/620; 708/501; 712/11; 712/10] | 129 Claims |
| 1. A reconfigurable chip, comprising:
a plurality of data modification units that are interconnected at least two-dimensionally and runtime reconfigurable in function
and interconnection, wherein at least some of the data modification units are arithmetic logic cells that each:
has three inputs A, B, and C adapted for feeding to the respective arithmetic logic cell respective ones of three data words
A, B, and C on respective ones of the three inputs A, B, and C; and
is adapted for performing within the respective arithmetic logic cell an operation of the data word A× the data word B+ the
data word C;
registers adapted for receiving output data of one of the plurality of modification units and feeding the output data back
for further processing in the modification unit;
registers adapted for delaying arrival of data at respective ones of the plurality of modification units to synchronize the
arrival of the data with an arrival of other data at the respective modification units; and
multiplexers adapted for selectively bypassing registers of the reconfigurable chip to allow for an orderly data processing
in runtime-delayed data;
wherein the chip is one of a processing chip and a Field Programmable Gate Array chip.
|