| US 7,595,531 B2 | ||
| Semiconductor device | ||
| Hisao Kawasaki, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 22, 2007, as Appl. No. 11/843,332. | ||
| Claims priority of application No. 2006-250516 (JP), filed on Sep. 15, 2006. | ||
| Prior Publication US 2008/0067558 A1, Mar. 20, 2008 | ||
| Int. Cl. H01L 29/49 (2006.01); H01L 29/78 (2006.01) | ||
| U.S. Cl. 257—343 [257/141; 257/E29.152] | 7 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate having an operation layer on a top surface thereof;
a source electrode and a drain electrode disposed on the operation layer, current flowing from the source electrode to the
drain electrode through the operation layer;
a gate electrode disposed between the source electrode and the drain electrode; and
a field plate electrode coupled to the gate electrode and disposed on an insulating film deposited between the gate electrode
and the drain electrode, wherein
at least a part of the gate electrode is disposed in a gate recess formed in the operation layer, the field plate electrode
is apart from the gate electrode by a predetermined distance, and at least a part of the field plate electrode is disposed
in a field plate recess formed in the operation layer, wherein a depth of the field plate recess is substantially equal to
a depth of the gate recess, the depth is a distance, from the top surface to a bottom, substantially perpendicular to the
current flow.
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