| US 7,595,529 B2 | ||
| Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same | ||
| Bong-Soo Kim, Gyeonggi-do (Korea, Republic of); Hyeong-Sun Hong, Gyeonggi-do (Korea, Republic of); Soo-Ho Shin, Gyeonggi-do (Korea, Republic of); and Ho-In Ryu, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jul. 18, 2008, as Appl. No. 12/176,263. | ||
| Application 12/176263 is a continuation of application No. 11/852940, filed on Sep. 10, 2007. | ||
| Claims priority of application No. 10-2007-0017585 (KR), filed on Feb. 21, 2007; and application No. 10-2007-0019755 (KR), filed on Feb. 27, 2007. | ||
| Prior Publication US 2008/0277795 A1, Nov. 13, 2008 | ||
| Int. Cl. H01L 21/768 (2006.01) | ||
| U.S. Cl. 257—330 [257/E23.145; 257/E21.585; 438/637] | 30 Claims |
| 4. A semiconductor integrated circuit device comprising:
a semiconductor substrate having an active region and an isolation layer surrounding the active region;
first and second upper patterns respectively disposed in predetermined regions of the semiconductor substrate, the first upper
pattern protruding upward from a top surface of the active region and extending downward from the top surface of the active
region, the second upper pattern protruding upward from a top surface of the isolation layer and extending downward from the
top surface of the isolation layer;
a first lower pattern including a first buried plug disposed below the top surface of the active region to contact the first
upper pattern through one of the predetermined regions of the semiconductor substrate and a first buried capping pattern disposed
on the first buried plug and protruding from the top surface of the active region to surround the first upper pattern; and
a second lower pattern including a second buried plug disposed below the top surface of the isolation layer to be surrounded
by the second upper pattern through the remaining predetermined region of the semiconductor substrate to contact the second
upper pattern, and the a second buried capping pattern disposed on the second buried plug and protruding from the top surface
of the isolation layer to surround the second upper pattern,
wherein the first upper pattern has different widths on the first buried plug along a direction toward the top surface of
the active region, and wherein the second upper pattern has the same width on the second buried plug along a direction toward
the top surface of the isolation layer.
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