| US 7,595,522 B2 | ||
| Nonvolatile semiconductor memory | ||
| Yuji Takeuchi, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 01, 2006, as Appl. No. 11/565,822. | ||
| Claims priority of application No. 2005-349045 (JP), filed on Dec. 02, 2005. | ||
| Prior Publication US 2007/0126046 A1, Jun. 07, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01) | ||
| U.S. Cl. 257—298 [257/288; 257/314; 438/201; 438/288] | 8 Claims |
| 1. A nonvolatile semiconductor memory, comprising:
a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on
a semiconductor substrate;
an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of said floating
gate electrode; and
a control gate electrode formed on said floating gate electrode via said inter-gate insulating film,
wherein a portion from the upper surface of said floating gate electrode to at least a middle of the portion of the side surface
which is covered with said inter-gate insulating film has a shape in which, toward the upper surface, an inclination angle
of the side surface to a direction perpendicular to a surface of said semiconductor substrate increases, unlike the other
portion of the side surface.
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