| US 7,595,251 B2 | ||
| Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby | ||
| Min-Hee Cho, Yongin-si (Korea, Republic of); Yoo-Sang Hwang, Suwon-si (Korea, Republic of); and Byung-Hyun Lee, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Dec. 01, 2008, as Appl. No. 12/325,694. | ||
| Application 12/325694 is a division of application No. 11/232666, filed on Sep. 22, 2005, granted, now 7,473,619. | ||
| Claims priority of application No. 10-2004-0076612 (KR), filed on Sep. 23, 2004. | ||
| Prior Publication US 2009/0087962 A1, Apr. 02, 2009 | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—401 [438/253; 257/E21.001] | 9 Claims |
| 1. A method of fabricating a semiconductor device comprising:
providing a semiconductor substrate having a scribe lane region and a cell region;
forming an etch barrier pattern and a gate pattern on the scribe lane region and the cell region respectively;
forming a first interlayer insulating layer to cover the etch barrier pattern and the gate pattern;
forming a preliminary alignment key pattern and a bit line pattern on the first interlayer insulating layer of the scribe
lane region and the cell region respectively;
forming a second interlayer insulating layer to cover the preliminary alignment key pattern and the bit line pattern; and
patterning the second interlayer insulating layer and the first interlayer insulating layer to expose the etch barrier pattern,
thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening
in the cell region.
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