| US 7,595,246 B2 | ||
| Methods of manufacturing field effect transistors having elevated source/drain regions | ||
| Min-Gu Kang, Seoul (Korea, Republic of); Ki-Hong Kim, Gyeonggi-do (Korea, Republic of); Jin-Bum Kim, Seoul (Korea, Republic of); Jung-Yun Won, Gyeonggi-do (Korea, Republic of); and In-Sun Jung, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Dec. 08, 2006, as Appl. No. 11/636,139. | ||
| Claims priority of application No. 10-2005-0121444 (KR), filed on Dec. 12, 2005. | ||
| Prior Publication US 2007/0134880 A1, Jun. 14, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—300 [257/E21.43] | 17 Claims |
| 1. A method of manufacturing a field effect transistor, comprising:
forming a gate pattern on a substrate;
forming a gate spacer on a sidewall of the gate pattern;
forming a first layer from a surface of the substrate and contacting the gate spacer using a first selective epitaxial growth
(SEG) process at a first temperature; and
forming a second layer from a surface of the first layer and contacting the gate spacer using a second SEG process at a second
temperature lower than the first temperature, the first and second layers defining elevated source/drain regions,
wherein forming the first layer comprises introducing a first source gas at a first flow rate for a first duration and wherein
forming the second layer comprises introducing a second source gas at a second flow rate greater than the first flow rate
for a second duration shorter than the first duration.
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