| US 7,594,215 B2 | ||
| Method and system for optimized automated IC package pin routing | ||
| Ken Wadland, Grafton, Mass. (US); Joe Morrison, Apalachin, N.Y. (US); and Julie Blumenthal, Waltham, Mass. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Apr. 21, 2005, as Appl. No. 11/112,868. | ||
| Claims priority of provisional application 60/629804, filed on Nov. 20, 2004. | ||
| Prior Publication US 2006/0112366 A1, May 25, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01); H03K 17/693 (2006.01) | ||
| U.S. Cl. 716—15 [716/12; 716/13; 716/14] | 46 Claims |
| 1. A method for improving the routability of one or more nets of an electronic circuit design, comprising:
receiving data of a ball grid array (BGA), including pin location information;
receiving net data, including net position information;
associating net position information with pin location information such that connection paths are identified;
determining whether there exists an intersection among the connection paths by traversing one or more rings;
determining whether reassignment of a net position relative to a pin location would result in at least one of:
an elimination of the intersection among the connection paths,
a shorter connection path, and
an resolution of an overloaded channel by moving one or more of the connection paths to another channel with available capacity;
creating or updating a routing solution for the electronic circuit design by modifying at least one of said net data and said
data of the ball grid array based at least in part on the act of determining whether there exists an intersection, wherein
the act of creating or updating the routing solution is performed by a computer processor; and storing the routing solution
on a computer readable storage medium or a storage device or displaying the routing solution on a display apparatus.
|