| US 7,594,214 B1 | ||
| Maximum flow analysis for electronic circuit design | ||
| Jeffrey Scott Salowe, Cupertino, Calif. (US); and Steven Lee Pucci, Los Gatos, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Aug. 07, 2006, as Appl. No. 11/500,756. | ||
| Application 11/500756 is a division of application No. 10/342828, filed on Jan. 14, 2003, granted, now 7,089,526. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/12] | 32 Claims |
| 1. A method for performing maximum flow analysis on a portion of an integrated circuit layout, comprising:
identifying a portion of an integrated circuit layout to analyze;
tessellating the portion of the integrated circuit layout to form a configuration of space tiles, wherein the configuration
of space tiles are based at least in part upon an object in the tessellated portion of the integrated circuit layout;
analyzing the configuration of space tiles;
determining by a computer processor of a computer aided design tool or of a electronic design automation system a maximum
flow through the portion of the integrated circuit layout based at least in part upon results for analyzing the configuration
of space tiles;
generating a routing path based at least in part upon the results for determining the maximum flow; and
routing an integrated circuit for fabrication based at least in part upon the routing path.
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