| US 7,594,208 B1 | ||
| Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage | ||
| Terry Borer, Toronto (Canada); Ian Chesal, Toronto (Canada); James Schleicher, Santa Clara, Calif. (US); David Mendel, Sunnyvale, Calif. (US); Mike Hutton, Mountain View, Calif. (US); Boris Ratchev, Sunnyvale, Calif. (US); Yaska Sankar, San Jose, Calif. (US); Babette van Antwerpen, Mountain View, Calif. (US); Gregg Baeckler, San Jose, Calif. (US); Richard Yuan, Cupertino, Calif. (US); Stephen Brown, Toronto (Canada); Vaughn Betz, Toronto (Canada); and Kevin Chan, Scarborough (Canada) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Dec. 13, 2006, as Appl. No. 11/610,392. | ||
| Application 11/610392 is a continuation of application No. 10/625505, filed on Jul. 22, 2003, granted, now 7,181,703. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 716—5 [716/4; 716/6; 716/18; 703/13; 703/14] | 31 Claims |
| 1. A method in a computer system for compiling a design for an integrated circuit, the method comprising:
performing multiple compilations of the design, each compilation comprising:
placing and routing the design on the integrated circuit; and
performing a timing analysis on the placed and routed design;
each compilation using a set of input parameters, each input parameter having a value from a series of automatically selected
values;
each compilation using the timing analysis to generate output values for an output metric of the placed and routed design;
concluding the compilations when a stopping criterion has been reached;
for each group of compilations having a common value for an input parameter, calculating an average output value for the output
metric;
selecting the group having an optimum average output value; and
using the common value for the input parameter for the selected group to compile the design on the integrated circuit.
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