| US 7,594,206 B2 | ||
| Fault detecting method and layout method for semiconductor integrated circuit | ||
| Takaki Yoshida, Ibaraki (Japan); and Reisuke Shimoda, Mishima-gun (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Apr. 24, 2006, as Appl. No. 11/409,033. | ||
| Application 11/409033 is a division of application No. 09/697305, filed on Oct. 27, 2000, granted, now 7,065,690. | ||
| Claims priority of application No. 11-307872 (JP), filed on Oct. 29, 1999. | ||
| Prior Publication US 2006/0236184 A1, Oct. 19, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 11/22 (2006.01); G01R 31/26 (2006.01); G01R 31/02 (2006.01); G01R 31/28 (2006.01) | ||
| U.S. Cl. 716—4 [716/2; 716/8; 716/12; 716/21; 703/14; 714/25; 714/33; 714/37; 714/741; 702/59; 324/527; 324/537] | 10 Claims |
| 1. A computer-implemented layout method for a semiconductor integrated circuit, comprising:
omitting from a fault list faults that are difficult to detect; and
performing by a computer mask layout and wiring of a semiconductor integrated circuit based on a remaining part of the fault
list.
|