US 7,594,145 B2
Improving performance of a processor having a defective cache
Tohru Ishihara, Fukuoka (Japan); and Farzan Fallah, San Jose, Calif. (US)
Assigned to Fujitsu Limited, Kanagawa (Japan)
Filed on May 31, 2006, as Appl. No. 11/421,365.
Prior Publication US 2007/0294587 A1, Dec. 20, 2007
Int. Cl. G06F 11/00 (2006.01)
U.S. Cl. 714—47  [714/8; 714/42; 714/44; 711/141; 711/144; 711/210] 12 Claims
OG exemplary drawing
 
1. A method for improving performance of a processor having a defective cache, the method comprising:
accessing first object code of an application program; and
generating second object code of the application program from the first object code, the generation of the second object code taking into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache to keep a total number of cache misses below a predefined threshold.