| US 7,594,099 B2 | ||
| Processor executing SIMD instructions | ||
| Tetsuya Tanaka, Soraku-gun (Japan); Hazuki Okabayashi, Hirakata (Japan); Taketo Heishi, Osaka (Japan); Hajime Ogawa, Suita (Japan); Tsuneyuki Suzuki, Takatsuki (Japan); Tokuzo Kiyohara, Osaka (Japan); Takeshi Tanaka, Neyagawa (Japan); Hideshi Nishida, Nishinomiya (Japan); and Masaki Maeda, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Aug. 31, 2007, as Appl. No. 11/896,368. | ||
| Application 11/896368 is a division of application No. 10/668358, filed on Sep. 24, 2003, granted, now 7,281,117. | ||
| Claims priority of application No. 2002-280077 (JP), filed on Sep. 25, 2002. | ||
| Prior Publication US 2008/0046687 A1, Feb. 21, 2008 | ||
| Int. Cl. G06F 9/305 (2006.01) | ||
| U.S. Cl. 712—223 | 2 Claims |
| 1. A processor for decoding and executing instructions, comprising:
a decoding unit configured to decode an instruction; and
an execution unit configured to execute the instruction based on a result of the decoding performed by the decoding unit,
wherein the execution unit, when the decoding unit decodes an add instruction including operands specifying first data and
second data, generates (i) a result obtained by adding the first data, the second data, and 1 when the first data is zero
or positive, and (ii) a result obtained by adding the first data and the second data when the first data is negative,
wherein the first data is an object of rounding away from zero, and
wherein the second data specifies a digit in the first data to be an object of rounding away from zero.
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