	US 7,593,872 B2
	Method and system for designing a probe card
Benjamin N. Eldridge, Danville, Calif. (US); Mark W. Brandemuehl, Mountain View, Calif. (US); Stefan Graef, Milpitas, Calif. (US); and Yves Parent, San Francisco, Calif. (US)
Assigned to FormFactor, Inc., Livermore, Calif. (US)
Filed on Aug. 15, 2006, as Appl. No. 11/464,760.
Application 11/464760 is a division of application No. 10/810758, filed on Mar. 26, 2004, granted, now 7,092,902.
Application 10/810758 is a continuation of application No. 09/954617, filed on Sep. 17, 2001, granted, now 6,714,828.
Prior Publication US 2006/0294008 A1, Dec. 28, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 30/00 (2006.01)

U.S. Cl. 705—26 [700/96; 700/97; 700/117; 700/180; 324/761; 709/203]

16 Claims

1. A method performed at a probe card manufacturer server computer of designing a probe card, wherein said probe card provides an interface for test signals between a tester and a semiconductor device to be tested and said probe card comprises tester contacts for making electrical connections with said tester, probes for making electrical connections with terminals of said semiconductor device, and electrical paths connecting ones of said tester contacts with ones of said probes, said method comprising:

receiving at said probe card manufacturer server computer from a remotely located customer computer device information describing said semiconductor device;

receiving at said probe card manufacturer server computer from said remotely located customer computer probe card information describing said probe card;

generating at said probe card manufacturer server computer from said device information and said probe card information a verification package that includes a proposed design of said probe card for testing said semiconductor device;

electronically determining at said probe card manufacturer server computer an acceptability of said proposed design of said probe card; and

communicating from said probe card manufacturer server computer to said customer computer said verification package and said electrically generated acceptability of said proposed design.