US 7,593,831 B2
Method and apparatus for testing delay lines
Werner Bachhuber, München (Germany); Osman Doertok, München (Germany); and Parag Parikh, Allentown, Pa. (US)
Assigned to Agere Systems Inc., Allentown, Pa. (US)
Filed on Aug. 04, 2006, as Appl. No. 11/499,363.
Prior Publication US 2008/0033678 A1, Feb. 07, 2008
Int. Cl. G04F 8/00 (2006.01); H03H 11/26 (2006.01)
U.S. Cl. 702—176  [327/261] 16 Claims
OG exemplary drawing
 
1. A circuit for testing a delay module having an input, an output, and control lines to control delay of said delay module, said circuit comprising:
an inverter chain having an output that is coupled to said input of the delay module to form a ring oscillator that oscillates at a frequency dependent upon setting of said control lines;
a counter having an input that is coupled to said output of said delay module and configured to generate a plurality of counts in response to settings of said control lines;
a first register having an input that is coupled to an output of said counter and configured to store a first count of said plurality of counts; and
a comparator having an input that is coupled to an output of said counter and an input that is coupled to an output of said first register, and configured to compare a second count of said plurality of counts output from said counter with said first count stored in the register to determine whether said delay module is operating correctly.