a first circuit to output a first signal having a first phase delay and a second signal having a second phase delay; and

a phase mixer coupled to receive the first and second signals from the first circuit, the phase mixer including:

multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal, the current driver outputs of the current drivers coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from a selectable weighted combination of the first and second phase delays; and

multiple first multiplexers each coupled to one of the current drivers, the first multiplexers each coupled to receive the first and second signals and coupled to independently selectively pass either the first signal or the second signals to the current driver input of a corresponding one of the current drivers, the first multiplexers each responsive to a phase mixer select (“PMSEL”) signal to collectively set the selectable weighted combination of the first and second phase delays.