| US 7,593,283 B2 | ||
| Semiconductor memory device | ||
| Nak-Kyu Park, Kyoungki-do (Korea, Republic of) | ||
| Assigned to Hynix Semiconductor, Inc., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jun. 29, 2007, as Appl. No. 11/822,002. | ||
| Claims priority of application No. 10-2006-0095181 (KR), filed on Sep. 28, 2006. | ||
| Prior Publication US 2008/0084776 A1, Apr. 10, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.03 [365/193; 365/189.04; 365/189.14; 365/189.15; 365/189.16] | 17 Claims |
| 1. A semiconductor memory device, comprising:
a global input/output line;
a first global core line;
a second global core line;
a global core line controller disposed between the first global core line and the second global core line;
a first bank coupled to the global core line controller through the first global core line; and
a second bank coupled to the global core line controller through the second global core line,
wherein the global core line controller includes
a read/write strobe signal activating unit configured to receive read/write information and a strobe signal for a column operation
to output a read strobe signal and a write strobe signal, the read strobe signal and the write strobe signal being activated
in a read operation and a write operation, respectively.
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