	US 7,593,268 B2
	Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
Volker Hecht, Barsinghausen (Germany); John McCollum, Saratoga, Calif. (US); and Robert M. Salter, III, Saratoga, Calif. (US)
Assigned to Actel Corporation, Mountain View, Calif. (US)
Filed on Dec. 06, 2006, as Appl. No. 11/567,625.
Application 11/567625 is a continuation of application No. 11/171489, filed on Jun. 29, 2005, granted, now 7,161,841, filed on Jan. 09, 2007.
Prior Publication US 2007/0091683 A1, Apr. 26, 2007
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01)

U.S. Cl. 365—185.29 [365/185.28]

6 Claims

1. A method for operating a non-volatile memory switch in an FPGA integrated circuit including a first p-well region coupled to ground; an n-channel MOS transistor disposed in the first p-well region, a second p-well region disposed within an n-well and electrically isolated from the first p-well region, and a non-volatile memory switch disposed in the second p-well region, the non-volatile memory switch having a source/drain region coupled to a drain of the n-channel MOS transistor, a source coupled to the second p-well, and a gate, the method comprising;

coupling the second p-well to ground when the integrated circuit is in an operating mode and to V_CCwhen the integrated circuit is in a mode in which the non-volatile memory switch is to be erased; and

coupling the n-well containing the second p-well to a potential of at least V_CCwhen the integrated circuit is in a mode in which the non-volatile memory switch is to be erased.