| US 7,593,261 B2 | ||
| EEPROM devices and methods of operating and fabricating the same | ||
| Geun-sook Park, Suwon-si (Korea, Republic of); Sang-bae Yi, Seoul (Korea, Republic of); Soo-cheol Lee, Seoul (Korea, Republic of); Ho-ik Hwang, Seoul (Korea, Republic of); and Tae-jung Lee, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Dec. 22, 2006, as Appl. No. 11/643,837. | ||
| Claims priority of application No. 10-2005-0127770 (KR), filed on Dec. 22, 2005. | ||
| Prior Publication US 2007/0145459 A1, Jun. 28, 2007 | ||
| Int. Cl. G11C 11/03 (2006.01) | ||
| U.S. Cl. 365—185.05 [365/185.18; 365/185.26; 365/185.27] | 20 Claims |
| 1. An electrically erasable and programmable read-only memory (EEPROM) comprising:
a semiconductor substrate including spaced apart first, second and third active regions;
a common floating gate traversing over the first through third active regions;
source/drain regions formed in the third active region on opposite sides of the floating gate;
a first interconnect connected to the first active region;
a second interconnect connected to the second active region;
a third interconnect connected to either one of the source/drain regions;
a first well disposed within the semiconductor substrate of the first active region; and
first impurity regions formed in the first active region on opposite sides of the floating gate.
|