US 7,593,249 B2
Memory device for protecting memory cells during programming
Luca G. Fasoli, San Jose, Calif. (US); and Tyler Thorp, Sunnyvale, Calif. (US)
Assigned to Sandisk 3D LLC, Milpitas, Calif. (US)
Filed on Jun. 17, 2008, as Appl. No. 12/140,991.
Application 12/140991 is a division of application No. 11/552426, filed on Oct. 24, 2006, granted, now 7,391,638.
Prior Publication US 2008/0247213 A1, Oct. 09, 2008
Int. Cl. G11C 16/24 (2006.01)
U.S. Cl. 365—105  [365/185.02; 365/185.23; 365/185.28] 39 Claims
OG exemplary drawing
 
10. A memory device comprising:
a memory array including a plurality of layers of memory cells stacked vertically above one another in a single chip;
a detection circuit operative to detect, while a memory cell of the memory array is being programmed, when the memory cell is in a programmed state; and
a memory cell protection circuit coupled to said detection circuit and the memory, said memory cell protection circuit being operative to protect the memory cell of the memory array against excessive electrical energy at least while the memory cell is being programmed.