| US 7,592,851 B2 | ||
| High performance pseudo dynamic pulse controllable multiplexer | ||
| Yuen H. Chan, Poughkeepsie, N.Y. (US); Ann H. Chen, Poughquag, N.Y. (US); Antonio R. Pelella, Highland Falls, N.Y. (US); and Shie-ei Wang, Wappingers Falls, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jan. 29, 2008, as Appl. No. 12/21,454. | ||
| Prior Publication US 2009/0189675 A1, Jul. 30, 2009 | ||
| Int. Cl. H03K 17/00 (2006.01) | ||
| U.S. Cl. 327—407 [327/408; 327/409; 327/410; 365/189.02; 365/230.02] | 14 Claims |
| 1. A dynamic multiplexer for generating a late select pulse signal in a set associative cache memory, comprising in combination:
a plurality of pull down transistor pairs coupled in parallel between a pre-charged node and an evaluation node;
said late select output coupled to said pre-charged node;
a first restore transistor switch and a second restore transistor switch connected in series between a pre-charge voltage
source and said pre-charge node;
an evaluation transistor switch coupling said evaluation node to common sink;
a clock signal having leading edge and a trailing edge;
a delay circuit coupled having a delay circuit input and a delay circuit output;
said clock signal coupled to said delay circuit input and generating a delayed clock signal having a delayed leading edge
and a delayed trailing edge at said delay circuit output;
said clock signal coupled to said first restore transistor and said evaluation transistor so that the leading edge of said
clock signal turns off said first restore transistor and turns on said evaluation transistor, and said trailing edge turns
on said first restore transistor and turns off said evaluation transistor;
said delayed clock signal coupled to said second restore transistor switch so that the delayed leading edge turns off said
second restore transistor switch and said delayed trailing edge turns on said second restore transistor;
whereby an output pulse is generated at said output whose pulse width is established by the interval between the leading edge
of said clock pulse and said delayed trailing edge.
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