	US 7,592,837 B2
	Low leakage and data retention circuitry
Barry A. Hoberman, Cupertino, Calif. (US); Daniel L. Hillman, San Jose, Calif. (US); William G. Walker, Saratoga, Calif. (US); John M. Callahan, San Ramon, Calif. (US); Michael A. Zampaglione, San Jose, Calif. (US); and Andrew Cole, Sunnyvale, Calif. (US)
Assigned to MOSAID Technologies Corporation, Ottawa (Canada)
Filed on Sep. 19, 2008, as Appl. No. 12/284,311.
Application 11/732181 is a division of application No. 11/041687, filed on Jan. 20, 2005, granted, now 7,227,383.
Application 12/284311 is a continuation of application No. 11/998725, filed on Nov. 30, 2007, granted, now 7,443,197.
Application 11/998725 is a continuation of application No. 11/732181, filed on Apr. 02, 2007, granted, now 7,348,804.
Claims priority of provisional application 60/546574, filed on Feb. 19, 2004.
Claims priority of provisional application 60/586565, filed on Jul. 09, 2004.
Prior Publication US 2009/0027080 A1, Jan. 29, 2009
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/0175 (2006.01)

U.S. Cl. 326—68 [326/21]

63 Claims

1. An integrated circuit comprising:

terminals including a common ground terminal and first and second power supply terminals;

a level shifter configured to translate binary data from voltage levels defined by said first power supply terminal and said common ground terminal, to voltage levels defined by said second power supply terminal and said common ground terminal, said level shifter having a sleep transistor, input transistors, and cross-coupled output latching devices between said common ground terminal and an output terminal, said sleep transistor in series with an electrical connection to said common ground terminal, and said input transistors driven by inputs at voltage levels defined by said first power supply terminal and said common ground terminal; and

power management circuitry configured to control power consumed by said level shifter using said sleep transistor.