| US 7,592,668 B2 | ||
| Charge balance techniques for power devices | ||
| Christopher Boguslaw Kocon, Mountain Top, Pa. (US) | ||
| Assigned to Fairchild Semiconductor Corporation, South Portland, Me. (US) | ||
| Filed on Mar. 30, 2006, as Appl. No. 11/396,239. | ||
| Prior Publication US 2007/0228490 A1, Oct. 04, 2007 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—335 [257/341] | 7 Claims |
| 1. A charge balance semiconductor power device, comprising:
an active area comprising a plurality of cells capable of conducting current when biased in a conducting state;
a non-active perimeter region surrounding the active area, wherein no current flows through the non-active perimeter region
when the plurality of cells are biased in the conducting state; and
alternately arranged strips of first conductivity type pillars and strips of second conductivity type pillars formed in a
silicon region of the second conductivity type, the strips of first conductivity type pillars having a depth, a width and
a length, the alternately arranged strips of first and second conductivity type extending along their length through both
the active area and the non-active perimeter region, wherein each of the strips of first conductivity type pillars includes
a discontinuity along its length forming a portion of a strip of second conductivity type region extending in the non-active
perimeter region perpendicular to the strips of first conductivity type pillars.
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