a substrate including a cell region and a peripheral circuit region;

a cell device isolation layer disposed on the cell region of the substrate to define a cell active region;

a floating gate including a lower floating gate and an upper floating gate sequentially stacked on the cell active region wherein the upper floating gate includes a flat portion disposed on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer, and a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions is larger than a width of a lower portion of the space;

a tunnel insulation pattern interposed between the floating gate and the cell active region;

a control gate electrode disposed on the floating gate; and

a blocking insulation pattern interposed between the control gate electrode and the floating gate;

a peripheral device isolation layer formed on the peripheral region to define a peripheral active region;

a peripheral gate electrode including a lower gate electrode and an upper gate electrode sequentially stacked on the peripheral active region, the upper gate electrode being connected with the lower gate electrode; and

a peripheral gate insulation pattern interposed between the peripheral gate electrode and the peripheral active region,

wherein the lower gate electrode comprises,

a first lower gate disposed on the peripheral gate insulation pattern,

a second lower gate including a peripheral flat portion disposed on the first lower gate and a pair of peripheral wall portions extending upward from both edges of the peripheral flat portion adjacent to the peripheral device isolation layer, and

a third lower gate filling a hollow region surrounded by the peripheral flat portion and the pair of peripheral wall portions.