| US 7,592,625 B2 | ||
| Semiconductor transistor with multi-level transistor structure and method of fabricating the same | ||
| Han-Byung Park, Seongnam-si (Korea, Republic of); Hoon Lim, Seoul (Korea, Republic of); and Soon-Moon Jung, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Aug. 11, 2006, as Appl. No. 11/502,397. | ||
| Claims priority of application No. 10-2005-0074220 (KR), filed on Aug. 12, 2005. | ||
| Prior Publication US 2007/0047371 A1, Mar. 01, 2007 | ||
| Int. Cl. H01L 31/112 (2006.01) | ||
| U.S. Cl. 257—67 [257/903] | 13 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate including a peripheral region and a cell array region, wherein the semiconductor substrate in the
cell array region is recessed lower than the substrate in the peripheral region, and a surface of the cell array region is
an etched surface;
a plurality of cell transistor layers stacked on the etched surface of the cell array region; and
a plurality of peripheral circuit transistors formed on the peripheral region of the semiconductor substrate.
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