	US 7,592,265 B2
	Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor
Meng-Jun Wang, Taichung County (Taiwan); Yi-Hsing Chen, Changhua County (Taiwan); Min-Chieh Yang, Kao-Hsiung (Taiwan); and Jiunn-Hsiung Liao, Tainan Hsien (Taiwan)
Assigned to United Microelectronics Corp., Hsin-Chu (Taiwan)
Filed on Jan. 04, 2007, as Appl. No. 11/620,028.
Prior Publication US 2008/0164526 A1, Jul. 10, 2008
Int. Cl. H01L 21/302 (2006.01); H01L 21/461 (2006.01)

U.S. Cl. 438—736 [438/950; 438/947; 438/671; 257/E21.488; 257/E21.492; 257/E21.483; 216/51; 216/47]

20 Claims

1. A method of trimming a hard mask layer, comprising:

providing a substrate and a hard mask layer on said substrate;

forming a multi-layer stack comprising at least a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer on said hard mask layer;

patterning said top photo resist layer;

etching said silicon photo resist layer by using said patterned top photo resist layer as an etching mask to pattern said silicon photo resist layer to form a first opening of a first width on the bottom thereof;

removing said top photo resist layer;

etching said bottom photo resist layer sequentially by using said patterned silicon photo resist layer as an etching mask;

etching said hard mask layer sequentially by using said patterned bottom photo resist layer as an etching mask to form a second opening of said first width; and

trimming said hard mask layer to make said second opening with a second width larger than said first width.