| US 7,591,067 B2 | ||
| Thermally enhanced coreless thin substrate with embedded chip and method for manufacturing the same | ||
| Chien-Hao Wang, Hsinchu County (Taiwan) | ||
| Assigned to Advanced Semiconductor Engineering Inc., Kaohsiung (Taiwan) | ||
| Filed on Dec. 27, 2006, as Appl. No. 11/616,288. | ||
| Claims priority of application No. 94147759 A (TW), filed on Dec. 30, 2005. | ||
| Prior Publication US 2007/0155057 A1, Jul. 05, 2007 | ||
| Int. Cl. H05K 1/18 (2006.01) | ||
| U.S. Cl. 29—832 [29/830; 29/852; 29/854; 29/846; 439/71; 361/729; 361/705; 361/783; 437/209; 437/211] | 11 Claims |
| 1. A method for manufacturing a thermally enhanced coreless thin substrate with an embedded chip, comprising:
providing a carrier metal layer;
attaching at least one chip to the carrier metal layer, wherein the chip has a plurality of electrodes;
forming a first dielectric layer on the carrier metal layer and covering the chip, wherein the first dielectric layer has
a plurality of through holes, the through holes are linked to the carrier metal layer, and the first dielectric layer exposes
the electrodes;
forming a first wiring layer on the first dielectric layer, wherein the first wiring layer comprises a plurality of first
trace lines and a plurality of second trace lines, the first trace lines is electrically connected to the carrier metal layer
via the through holes and the second trace lines are electrically connected to the electrodes; and
patterning the carrier metal layer so that the carrier metal layer comprises a heat sink portion attached to the chip.
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