US 11,758,740 B2
Three-dimensional semiconductor device and method of fabricating the same
Chang-Tsung Pai, Taichung (TW); Chiung-Lin Hsu, Taichung (TW); Yu-Ting Chen, Taichung (TW); Ming-Che Lin, Taichung (TW); and Chi-Ching Liu, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Apr. 7, 2021, as Appl. No. 17/224,152.
Claims priority of application No. 109116733 (TW), filed on May 20, 2020.
Prior Publication US 2021/0366986 A1, Nov. 25, 2021
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/30 (2023.02) [H10N 70/011 (2023.02); H10N 70/253 (2023.02); H10N 70/8265 (2023.02); H10N 70/841 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor device, comprising multiple semiconductor device layers on a substrate, wherein each of the semiconductor device layers comprises:
a first transistor, comprising:
a first stacked structure that is on the substrate, wherein the first stacked structure comprises a first insulating layer and a first gate conductor layer;
a first gate dielectric layer surrounding a sidewall of the first stacked structure;
a first semiconductor layer surrounding a sidewall of the first gate dielectric layer;
a first channel layer that is in the first semiconductor layer; and
a first source region and a first drain region that are on both sides of the first channel layer in the first semiconductor layer; and
a first resistive random access memory cell that is on a first sidewall of the first semiconductor layer of the first transistor and connected to the first drain region.