CPC H10B 63/30 (2023.02) [H10N 70/011 (2023.02); H10N 70/253 (2023.02); H10N 70/8265 (2023.02); H10N 70/841 (2023.02)] | 14 Claims |
1. A three-dimensional semiconductor device, comprising multiple semiconductor device layers on a substrate, wherein each of the semiconductor device layers comprises:
a first transistor, comprising:
a first stacked structure that is on the substrate, wherein the first stacked structure comprises a first insulating layer and a first gate conductor layer;
a first gate dielectric layer surrounding a sidewall of the first stacked structure;
a first semiconductor layer surrounding a sidewall of the first gate dielectric layer;
a first channel layer that is in the first semiconductor layer; and
a first source region and a first drain region that are on both sides of the first channel layer in the first semiconductor layer; and
a first resistive random access memory cell that is on a first sidewall of the first semiconductor layer of the first transistor and connected to the first drain region.
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