US 11,758,735 B2
Common-connection method in 3D memory
Meng-Han Lin, Hsinchu (TW); Chia-En Huang, Hsinchu County (TW); and Yi-Ching Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 25, 2021, as Appl. No. 17/185,229.
Prior Publication US 2022/0271048 A1, Aug. 25, 2022
Int. Cl. H10B 51/30 (2023.01); H01L 23/528 (2006.01); H10B 51/20 (2023.01); H10B 51/10 (2023.01)
CPC H10B 51/30 (2023.02) [H01L 23/528 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first drain/source structure extending in a first direction;
a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction;
a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction;
a first bit line extending in a third direction perpendicular to the first direction and the second direction, the first bit line disposed over the first drain/source structure in the first direction;
a common select line that includes a portion extending in the third direction and disposed over the second drain/source structure in the first direction;
a second bit line extending in the third direction and disposed over the third drain/source structure in the first direction;
a charge storage layer having at least a portion continuously extending along the second direction to couple to a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure; and
a channel that is interposed between the charge storage layer and the at least first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.