US 11,758,733 B2
3D memory multi-stack connection method
Chia-En Huang, Xinfeng Township (TW); Meng-Han Lin, Hsinchu (TW); and Ya-Hui Wu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 30, 2021, as Appl. No. 17/245,142.
Prior Publication US 2022/0352207 A1, Nov. 3, 2022
Int. Cl. H10B 51/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H01L 29/417 (2006.01)
CPC H10B 51/20 (2023.02) [H01L 29/41741 (2013.01); H01L 29/41775 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first memory array comprising:
a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings comprising a plurality of memory cells arranged along a vertical direction; and
a plurality of first conductive structures extending along the vertical direction;
wherein each of the plurality of first conductive structures comprises a first portion and a second portion;
wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and
wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.