US 11,758,729 B2
Three-dimensional memory device having a shielding layer and method for forming the same
Zongliang Huo, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Li Hong Xiao, Wuhan (CN); and Jun Chen, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Nov. 21, 2020, as Appl. No. 17/100,844.
Application 17/100,844 is a division of application No. 16/140,427, filed on Sep. 24, 2018, granted, now 11,043,506.
Application 16/140,427 is a continuation of application No. PCT/CN2018/093423, filed on Jun. 28, 2018.
Prior Publication US 2021/0104534 A1, Apr. 8, 2021
Int. Cl. G11C 5/06 (2006.01); H10B 43/40 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); G11C 16/06 (2006.01)
CPC H10B 43/40 (2023.02) [G11C 5/06 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); G11C 16/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a peripheral device on a first substrate;
forming a first interconnect layer comprising a first plurality of interconnect structures above the peripheral device on the first substrate;
forming a shielding layer comprising a conduction region above the first interconnect layer on the first substrate, wherein the conduction region of the shielding layer covers substantially an area of the plurality of interconnect structures in the first interconnect layer;
forming a first contact extending vertically through an isolation region of the shielding layer and in contact with the first interconnect layer, wherein the first contact is electrically isolated from conduction region by the isolation region;
forming an alternating conductor/dielectric stack and a plurality of memory strings each extending vertically through the alternating conductor/dielectric stack on a second substrate;
forming on the second substrate a second interconnect layer comprising a plurality of interconnect structures above the plurality of memory strings on the second substrate; and
bonding the first substrate and the second substrate in a face-to-face manner, such that the shielding layer is between the first interconnect layer and the second interconnect layer, and the first contact is in contact with the second interconnect layer.