CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53257 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/78642 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 40 Claims |
1. A thin-film NOR memory string formed above a planar surface of a semiconductor substrate, the semiconductor substrate including circuitry formed therein or thereon for supporting memory circuit operations, comprising:
a common source region and a common drain region each extending lengthwise along a first direction substantially perpendicular to the planar surface;
a plurality of channel regions, each being provided between and in contact with both the common drain region and the common source region;
a plurality of regions of charge-trapping material each provided associated with and in contact with a respective one of the channel regions; and
a plurality of gate electrodes that are spaced apart from each other and insulated from each other by a dielectric material, each gate electrode being positioned to be adjacent one of the channel regions, separated from that channel region by the associated region of charge-trapping material, each gate electrode extending lengthwise along a second direction substantially parallel the planar surface.
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