US 11,758,727 B2
Three-dimensional vertical nor flash thin-film transistor strings
Eli Harari, Saratoga, CA (US); and Tianhong Yan, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, Fremont, CA (US)
Filed on May 24, 2021, as Appl. No. 17/328,991.
Application 17/328,991 is a continuation of application No. 17/068,539, filed on Oct. 12, 2020, granted, now 11,049,879, issued on Jun. 29, 2021.
Application 17/068,539 is a continuation of application No. 16/899,266, filed on Jun. 11, 2020, granted, now 10,854,634, issued on Dec. 1, 2020.
Application 16/899,266 is a continuation of application No. 16/786,828, filed on Feb. 10, 2020, granted, now 10,720,448, issued on Jul. 21, 2020.
Application 16/786,828 is a continuation of application No. 16/593,642, filed on Oct. 4, 2019, granted, now 10,593,698, issued on Mar. 17, 2020.
Application 16/593,642 is a continuation of application No. 16/447,406, filed on Jun. 20, 2019, granted, now 10,475,812, issued on Nov. 12, 2019.
Application 16/447,406 is a continuation of application No. 16/252,301, filed on Jan. 18, 2019, granted, now 10,381,378, issued on Aug. 13, 2019.
Application 16/252,301 is a continuation in part of application No. 16/107,732, filed on Aug. 21, 2018, granted, now 10,249,370, issued on Apr. 2, 2019.
Claims priority of provisional application 62/630,214, filed on Feb. 13, 2018.
Claims priority of provisional application 62/625,818, filed on Feb. 2, 2018.
Prior Publication US 2021/0280604 A1, Sep. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/02 (2006.01); H10B 43/27 (2023.01); H01L 29/06 (2006.01); G11C 16/04 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01); G11C 16/30 (2006.01); H01L 29/786 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53257 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/78642 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 40 Claims
OG exemplary drawing
 
1. A thin-film NOR memory string formed above a planar surface of a semiconductor substrate, the semiconductor substrate including circuitry formed therein or thereon for supporting memory circuit operations, comprising:
a common source region and a common drain region each extending lengthwise along a first direction substantially perpendicular to the planar surface;
a plurality of channel regions, each being provided between and in contact with both the common drain region and the common source region;
a plurality of regions of charge-trapping material each provided associated with and in contact with a respective one of the channel regions; and
a plurality of gate electrodes that are spaced apart from each other and insulated from each other by a dielectric material, each gate electrode being positioned to be adjacent one of the channel regions, separated from that channel region by the associated region of charge-trapping material, each gate electrode extending lengthwise along a second direction substantially parallel the planar surface.