US 11,758,717 B2
Semiconductor memory devices with one-sided staircase profiles and methods of manufacturing thereof
Meng-Han Lin, Hsinchu (TW); and Chia-En Huang, Xinfeng Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 6, 2021, as Appl. No. 17/313,174.
Prior Publication US 2022/0359553 A1, Nov. 10, 2022
Int. Cl. H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor die, comprising:
providing a stack comprising a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other;
forming a first interface portion on a first end and a second interface portion on a second end of the semiconductor die opposite the first end in a first direction, each of the first interface portion and the second interface portion having a staircase profile in a vertical direction;
forming an array of device structures between the first interface portion and the second interface portion;
forming a plurality of first trenches through the stack in the first direction between each row of device structures included in the array of device structures, and a second trench through the stack in a second direction perpendicular to the first direction, with each of the plurality of first trenches being intersected by the second trench, the second trench dividing the array of devices structures into a first sub-array of devices structures included in a first device portion and a second sub-array of device structures included in a second device portion, the second device portion being electrically isolated from the first device portion;
forming a plurality of gate layers by replacing the plurality of sacrificial layers so as to form a first sub-array of memory devices in the first device portion and a second sub-array of memory devices in the second device portion; and
filling the plurality of first trenches and the second trench with an insulating material.